Phase change memory devices and fabrication methods thereof

ABSTRACT

In a memory device, at least one conductive contact having a width of less than, or equal to, about 30 nm may be formed on a first electrode. A dielectric layer may be formed on the sides of the at least one conductive contact, and a phase change material film may be formed on the conductive contact. A second electrode may be formed on the phase change material.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2005-0013143, filed on Feb. 17, 2005, in the KoreanIntellectual Property Office (KIPO), the entire contents of which areincorporated herein by reference.

BACKGROUND

1. Field of the Invention

Example embodiments of the present invention relate to phase changememory devices and fabrication methods thereof.

2. Description of the Related Art

Semiconductor memory devices may be volatile or nonvolatile memorydevices according to whether data is retained when powered off. Volatilememory devices include, for example, dynamic random access memories(DRAM), static random access memories (SDRAM), etc. Nonvolatile memorydevices include, for example, flash memory devices. Related art memorydevices represent logic or binary values “0” or “1” according to whetheror not an electric charge is stored therein. In one example, a DRAM mayrequire a higher charge storage capacity because it may need to berefreshed periodically. However, as charge storage capacity increases,so does surface area of a capacitor electrode of the DRAM. This maysuppress integration of the DRAM.

In another example, a flash memory cell has a gate pattern including agate insulating film, a floating gate, a dielectric film and a controlgate, which may be sequentially deposited on a semiconductor substrate.Data may be written in or erased from the flash memory cell by tunnelingof electric charges through the gate insulating film. To do so, anoperating voltage higher than a source voltage may be required, and theflash memory device may need to have an amplifier circuit for generatingvoltages necessary for the data writing/erasing operations.

An example memory, which may have nonvolatile/random accesscharacteristics, an increased integration degree and/or a simplestructure is a phase change memory device using phase change material.The phase change material may become an amorphous state or a crystallinestate according to strength of a current (e.g., joule's heat) providedthereto, and the amorphous phase change material may have an electricalconductivity different from that of the crystalline phase changematerial.

FIG. 1 is an example graph illustrating an operating method of a phasechange memory device. The graph of FIG. 1 may describe a method forwriting/erasing data to/from a phase change memory cell. In the graph, ahorizontal axis represents time and a vertical axis represents atemperature applied to a phase change material film.

Referring to FIG. 1, the phase change material film is phase-changedinto an amorphous state when heated during a time period T₁ attemperatures higher than its melting temperature T_(m) and cooledrapidly (curve I). The phase change material film is phase-changed intoa crystalline state when heated during a time period T₂ at temperaturesbetween a crystallizaton temperature T_(c) and the melting temperatureT_(m), and cooled slowly (curve II). The time period T₂ may be longerthan the time period T₁.

The amorphous phase change material film may have a higher resistancethan the crystalline phase change material film. Accordingly, whetherdata stored in the phase change memory cell is logic “1” or logic “0”may be determined by detecting a current flowing through the phasechange material film. The phase change material film may be comprised ofa chalcogenide or any other suitable substance having similar orsubstantially. similar properties. For example, the phase changematerial film may be comprised of a compound containing germanium (Ge),antimony (Sb), tellurium (Te) or any other suitable element, substanceor compound having similar, or substantially similar, properties.

FIG. 2 is a schematic sectional view illustrating a structure of arelated art phase change memory device.

Referring to FIG. 2, the related art phase change memory device mayinclude a lower electrode 10, an upper electrode 18, a thin phase changematerial film 16 interposed between the electrodes 10 and 18, and aconductive contact 14 electrically connecting the lower electrode 18with the phase change material film 16. Sides of the lower electrode 10and the conductive contact 14 may be formed within (e.g., buried) in aninsulation layer 12 and the lower electrode 10 may be electricallyconnected to a drain (D) region of a transistor 5. The upper electrode18 may be electrically connected to a bit line (BL). A gate electrode(G) of the transistor 5 may be electrically connected to a word line(WL).

In the example related art phase change memory device of FIG. 2, when acurrent flows between the lower electrode 10 and the upper electrode 18,a current having flowed through the conductive contact 14 may flowthrough a contact surface 20 into the phase change material film 16. Asa result, a crystalline state of phase change material around thecontact surface 20 may change. The strength of the current necessary forchanging the state of the phase change material may be proportional tothe area of the contact surface 20. For example, the necessary currentstrength may be decreased as the contact surface area is reduced.However, reduction of the widths and/or areas of contact surfaces ofconductive contacts may be limited due to the photolithographic processused to form the conductive contacts. This may result in lesserintegration of semiconductor devices.

SUMMARY OF THE INVENTION

Example embodiments of the present invention provide phase change memorydevices, and methods of fabricating the same, which may require a lowerdriving current pulse and/or consume less power.

A memory device according to an example embodiment of the presentinvention may include at least one conductive contact formed on a firstelectrode. The conductive contact may have a width of less than, orequal to, about 30 nm. A dielectric layer may be formed on the sides ofthe at least one conductive contact, and a phase change material filmmay be formed on the conductive contact. A second electrode may beformed on the phase change material film. A transistor may beelectrically connected to the first electrode. A phase change catalystmay be formed between the sides of the conductive contact and thedielectric layer, such that the phase change catalyst contacts the phasechange material film.

In a method for fabricating a phase change memory device according to anexample embodiment of the present invention, a first electrode may beformed on a semiconductor substrate, which may include a transistor. Atleast one conductive contact may be formed on the first electrode, andthe dielectric layer may be formed on first electrode such that thedielectric layer contacts the sides of the conductive contact. A phasechange material film and a second electrode may be formed on theconductive contact and the dielectric layer. The phase change materialfilm and the second electrode may be patterned.

In example embodiments of the present invention, a conductive contactlayer, a first mask layer and a second mask layer may be sequentiallyformed on the first electrode. The second mask layer may have a widthless than the first mask layer. An oxide layer may be formed on at leastone side of the second mask layer and may have a width less than, orequal to, about 30 nm. The second mask layer may be removed, and thefirst mask layer and the conductive contact layer may be etched to format least one stack. A dielectric layer may be formed on the at least onestack and the first electrode, and the dielectric layer and the at leastone stack may be planarized.

In a method of forming a memory device, according to another exampleembodiment of the present invention, a first electrode may be formed ona semiconductor substrate including a transistor. A conductive contactmay be formed on the first electrode, and a phase change catalyst may beformed on each side of the conductive contact. A dielectric layer may beformed on each side of the phase change catalyst, and a phase changematerial film and a second electrode may be formed on the conductivecontact and the first electrode. The phase change material film and thesecond electrode may be patterned.

In example embodiments of the present invention, the phase changecatalyst may include one of ZnS, ZnS+SiO₂, and Al₂O₃, the firstelectrode, the second electrode and/or the conductive contact may becomprised of materials including at least Ti. The dielectric layer mayinclude one of Si₃N₄ and TEOS oxide and/or the phase change materialfilm is formed to have a thickness of about 1000 Å.

In example embodiments of the present invention, the conductive contactlayer, a first mask layer and a second mask layer may be sequentiallyformed on the first electrode. The second mask layer may have a widthless than the first mask layer. An oxide layer may be formed on at leastone side of the second mask layer, the oxide layer having a width lessthan, or equal to, about 30 nm. The second mask layer may be removed andthe first mask layer and the conductive contact layer may be etched toform at least one stack. A phase change catalyst layer may be formed onthe first electrode and may cover the at least one stack. A portion ofthe phase change catalyst layer may be removed to form the phase changecatalyst on each side of the conductive contact, and a dielectric layercovering the at least one stack and remaining portion of the phasechange catalyst layer may be formed. The dielectric layer, the at leastone stack, and the phase change catalyst layer may be planarized.

In example embodiments of the present invention, the oxide layer may beformed by depositing an oxide layer on the first and second mask layers,and etching the oxide layer to form an oxide layer on at least one sideof the second mask layer. The oxide layer may be deposited to have athickness of about 20 nm to about 50 nm, inclusive, or to have athickness of less than, or equal to, about 30 nm. The oxide layer may bedeposited using chemical vapor deposition or atomic layer deposition.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more apparent by describing in detailthe example embodiments shown in the attached drawings in which:

FIG. 1 is an example graph illustrating an operating method of a relatedart phase change memory device;

FIG. 2 is a schematic sectional view illustrating a structure of arelated art phase change memory device;

FIG. 3 is a sectional view of a phase change memory device according toan example embodiment of the present invention; and

FIGS. 4A through 4I are sectional views illustrating a method forfabricating a phase change memory device according to an exampleembodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE PRESENT INVENTION

Various example embodiments of the present invention will now bedescribed more fully with reference to the accompanying drawings inwhich some example embodiments of the invention are shown. In thedrawings, the thicknesses of layers and regions are exaggerated forclarity.

Detailed illustrative embodiments of the present invention are disclosedherein. However, specific structural and functional details disclosedherein are merely representative for purposes of describing exampleembodiments of the present invention. This invention may, however, maybe embodied in many alternate forms and should not be construed aslimited to only the embodiments set forth herein.

Accordingly, while example embodiments of the invention are capable ofvarious modifications and alternative forms, embodiments thereof areshown by way of example in the drawings and will herein be described indetail. It should be understood, however, that there is no intent tolimit example embodiments of the invention to the particular formsdisclosed, but on the contrary, example embodiments of the invention areto cover all modifications, equivalents, and alternatives falling withinthe scope of the invention. Like numbers refer to like elementsthroughout the description of the figures.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of example embodiments of thepresent invention. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to asbeing “formed on” another element or layer, it can be directly orindirectly formed on the other element or layer. That is, for example,intervening elements or layers may be present. In contrast, when anelement or layer is referred to as being “directly formed on” to anotherelement, there are no intervening elements or layers present. Otherwords used to describe the relationship between elements or layersshould be interpreted in a like fashion (e.g., “between” versus“directly between”, “adjacent” versus “directly adjacent”, etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments of the invention. As used herein, the singular forms “a”,“an” and “the” are intended to include the plural forms as well, unlessthe context clearly indicates otherwise. It will be further understoodthat the terms “comprises”, “comprising,”, “includes” and/or“including”, when used herein, specify the presence of stated features,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the FIGS. Forexample, two FIGS. shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

FIG. 3 is a sectional view of a memory device according to an exampleembodiment of the present invention.

Referring to FIG. 3 a phase change memory device 100 may include a lowerelectrode 110 electrically connected to a transistor (not shown). Thetransistor may be integrated into or on a semiconductor substrate. Aninsulation layer 120 may be formed on the lower electrode 110, and acontact hole 122 may be formed in the insulation layer 120. A conductivecontact 130 may be formed (e.g., vertically formed) in the contact hole122.

A phase change catalyst 132 may be formed on each side of, or around,the conductive contact 130. A phase change material film 140 contactingthe conductive contact 130 maybe formed on the insulation layer 120. Anupper electrode 150 may be formed on the phase change material film 140.

The conductive contact 130 may be comprised of TiN, TiAIN or any othersuitable material with similar, or substantially similar, conductiveproperties, and may have a width of about 30 nm or less. In an exampleembodiment of the present invention, the upper electrode 150 and/or theconductive contact 130 may be formed to have a contact surface 134 ofabout 200 nm×20 nm there between. The contact surface 134 may have awidth of less than, or equal to, about 30 nm.

The phase change material film 140 may be comprised of a chalcogenide,or any other material with similar or substantially similar properties.Chalcogenide and similar substances are well known to those skilled inthe art. The phase change catalyst 132 may be comprised of, for example,ZnS, ZnS+SiO₂, or Al₂O₃, and may accelerate and/or improve a phasechange of the phase change material film 140. Reference numeral 142denotes an area in which the phase change material film 140 may bephase-changed in response to a current flow from, for example, theoutside.

FIGS. 4A through 4I are sectional views illustrating a method forfabricating a phase change memory device according to an exampleembodiment of the present invention. For the sake of brevity, a methodfor fabricating two memory cells, according to an example embodiment ofthe present invention, is illustrated in the drawings. However, it willbe understood that any number of memory cells may be fabricated usingexample embodiments of the present invention.

Referring first to FIG. 4A, a transistor (not shown) may be formed on asemiconductor substrate (not shown) using any conventional method. Alower electrode 210 may be formed and electrically connected to a drainregion of the transistor. A heat dissipation layer 220 may be formed onthe lower electrode 210. The lower electrode 210 may be comprised ofTiN, TiAIN or any other material or substance having similar orsubstantially similar properties. A first mask layer 230 may be formedon the heat dissipation layer 220. The first mask layer 230 may becomprised of Si₃N₄ or any other substance or material having similar orsubstantially similar properties. A second mask layer 232 having anetching speed different from that of the first mask layer 230 may beformed on the first mask layer 230. The second mask layer 232 may becomprised of SiGe or any other substance or material having similar orsubstantially similar properties. The second mask layer 232 may bepatterned to have a second width W2. The second width W2 may be set tocorrespond to a desired distance between two memory cells, and/or may beless than the width of the first mask layer 230.

Referring to FIG. 4B, an oxide layer 240 may be deposited on the firstmask layer 230 so as to cover the first and second mask layers 230 and232. The oxide layer 240 may be formed of SiO₂ or any other substance ormaterial having similar or substantially similar properties, and/or mayhave a thickness of about 20 nm.

Referring to FIG. 4C, an oxide layer 240A with a second width W2 may beformed on the both sides of the second mask layer 232 by patterning theoxide layer 240. The second width W2 may be determined using the abovedeposition process.

Referring to FIG. 4D, the second mask layer 232 between the two oxidelayers 240A may be removed using an etching agent that may etch thefirst mask layer 230 and the second mask layer 232 in different ratios.

Referring to FIG. 4E, the first mask layer 230 and/or the heatdissipation layer 220 may be etched (e.g., anisotropically etched) insequence with a mask of the oxide layer 240A. A resulting heatdissipation layer 220A may correspond to the conductive contact 130shown in FIG. 3. A phase change catalyst 250 may be deposited on thelower electrode 210 so as to cover a stack 242, which may include aconductive contact 220A, a first mask layer 230A and/or the oxide layer240A. The phase change catalyst 250 may be comprised of ZnS, ZnS+SiO₂,or Al₂O₃ or any other substance or material having similar, orsubstantially similar, properties. The phase change catalyst 250 may bedeposited using chemical vapor deposition (CVD), atomic layer deposition(ALD) or any other suitable deposition process.

Referring to FIG. 4F, the portion of the phase change catalyst 250 notcovering sides of the stack 242 may be etched (e.g., anisotropicallyetched) and removed. A dielectric layer 260 may be formed on the lowerelectrode 210 using CVD, ALD or any other suitable deposition processsuch that the dielectric layer 260 may cover the stack 242 and/or thephase change catalyst 250. The dielectric layer 260 may be formed ofSi₃N₄, TEOS oxide or any other substance or material having similar orsubstantially similar properties and/or may have a thickness of about 20to 50 nm, inclusive. The dielectric layer 260 may be formed to have athickness larger than at least a height of the conductive contact 220A.

Referring to FIG. 4G, the stack 242, the phase change catalyst 250and/or the dielectric suitable layer 260 may be planarized usingchemical mechanical polishing (CMP) or any other suitable polishingprocess so that the conductive contact 220A may be exposed.

Referring to FIG. 4H, a phase change material film 270 having athickness of about 1000 Å may be deposited on the lower electrode 210 soas to cover the conductive contact 220A, the phase change catalyst 250and/or the dielectric layer 260. An upper electrode 280 may be depositedon the phase change material film 270.

Referring to FIG. 4I, a phase change material film 270A and/or an upperelectrode 280A may be formed on the conductive contact 220A, and twomemory cells 290 may be formed by patterning (e.g., sequentiallypatterning) the upper electrode 280 and/or the phase change materialfilm 270. A discrete memory device may be produced through a singulationor any other suitable process.

Example embodiments of the present invention may provide a conductivecontact having a width of less than, or equal to, 30 nm, reduce acontact area between the conductive contact and the phase changematerial film, increase a current density at the contact area, and/orreduce the strength of a current applied to the memory device.

In example embodiments, the phase change material film may includechalcogenide alloys such as germanium-antimony-tellurium (Ge—Sb—Te),arsenic-antimony-tellurium (As—Sb—Te), tin-antimony-tellurium(Sn—Sb—Te), or tin-indium-antimony-tellurium (Sn—In—Sb—Te),arsenic-germanium-antimony-tellurium (As—Ge—Sb—Te). Alternatively, thephase change material film may include an element in GroupVA-antimony-tellurium such as tantalum-antimony-tellurium (Ta—Sb—Te),niobium-antimony-tellurium (Nb—Sb—Te) or vanadium-antimony-tellurium(V—Sb—Te) or an element in Group VA-antimony-selenium such astantalum-antimony-selenium (Ta—Sb—Se), niobium-antimony-selenium(Nb—Sb—Se) or vanadium-antimony-selenium (V—Sb—Se). Further, the phasechange material film may include an element in GroupVIA-antimony-tellurium such as tungsten-antimony-tellurium (W—Sb—Te),molybdenum-antimony-tellurium (Mo—Sb—Te), or chrome-antimony-tellurium(Cr—Sb—Te) or an element in Group VIA-antimony-selenium such astungsten-antimony-selenium (W—Sb—Se), molybdenum-antimony-selenium(Mo—Sb—Se) or chrome-antimony-selenium (Cr—Sb—Se).

Although the phase change material film is described above as beingformed primarily of ternary phase-change chalcogenide alloys, thechalcogenide alloy of the phase change material could be selected from abinary phase-change chalcogenide alloy or a quaternary phase-changechalcogenide alloy. Example binary phase-change chalcogenide alloys mayinclude one or more of Ga—Sb, In—Sb, In—Se, Sb₂—Te₃ or Ge—Te alloys;example quaternary phase-change chalcogenide alloys may include one ormore of an Ag—In—Sb—Te, (Ge—Sn)—Sb—Te, Ge—Sb—(Se—Te) or Te₈₁—Ge₁₅—Sb₂—S₂alloy, for example.

In an example embodiment, the phase change material film may be made ofa transition metal oxide having multiple resistance states, as describedabove. For example, the phase change material may be made of at leastone material selected from the group consisting of NiO, TiO₂, HfO,Nb₂O₅, ZnO, WO₃, and CoO or GST (Ge₂Sb₂Te₅) or PCMO(Pr_(x)Ca_(1−x)MnO₃).The phase change material film may be a chemical compound including oneor more elements selected from the group consisting of S, Se, Te, As,Sb, Ge, Sn, In and Ag.

While example embodiments of the present invention have beenparticularly shown and described with reference to the drawings, it willbe understood by those of ordinary skill in the art that various changesin form and details may be made therein without departing from thespirit and scope of the present invention as defined by the followingclaims.

1. A memory device comprising: a first electrode; at least oneconductive contact formed on the first electrode and having a width ofless than, or equal to, about 30 nm; a dielectric layer formed on thesides of the at least one conductive contact; a phase change materialfilm formed on the conductive contact; a second electrode formed on thephase change material film; and a transistor electrically connected tothe first electrode.
 2. The device of claim 1, further including a phasechange catalyst formed between the sides of the conductive contact andthe dielectric layer, such that the phase change catalyst contacts thephase change material film.
 3. The device of claim 2, wherein the phasechange catalyst includes one of ZnS, ZnS+SiO₂, and Al₂O₃.
 4. The memorydevice of claim 1, wherein the first electrode, the second electrode andthe conductive contact are comprised of materials including at least Ti.5. The memory device of claim 1, wherein the dielectric layer includesone of Si₃N₄ and TEOS oxide or the phase change material film is formedto have a thickness of about 1000 Å. 6-20. (canceled)